-
1 instruction cycle
= instruction execution cycleцикл исполнения команды, командный цикл1) последовательность шагов ЦП для исполнения команды. Обычная схема исполнения состоит из пяти шагов: выборка (fetch), декодирование (instruction decoding), выборка операндов (operand fetch), исполнение команды (ALU operation), запись результата (result writeback).Syn:2) время, затрачиваемое центральным процессором на исполнение одной команды. Зависит от быстродействия ОЗУ, тактовой частоты, разрядности (ширины) шины данных и архитектуры процессора.Англо-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. > instruction cycle
См. также в других словарях:
Micro-operation — In computer central processing units, micro operations (also known as a micro ops or μops) are detailed low level instructions used in some designs to implement complex machine instructions (sometimes termed macro instructions in this context).… … Wikipedia
computer — computerlike, adj. /keuhm pyooh teuhr/, n. 1. Also called processor. an electronic device designed to accept data, perform prescribed mathematical and logical operations at high speed, and display the results of these operations. Cf. analog… … Universalium
Instruction set — An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception… … Wikipedia
Tomasulo algorithm — The Tomasulo algorithm is a hardware algorithm developed in 1967 by Robert Tomasulo from IBM. It allows sequential instructions that would normally be stalled due to certain dependencies to execute non sequentially (out of order execution). It… … Wikipedia
Sum addressed decoder — In CPU design, a Sum Addressed Decoder or Sum Addressed Memory (SAM) Decoder is a method of reducing the latency of the CPU cache access. This is achieved by fusing the address generation sum operation with the decode operation in the cache… … Wikipedia
Adder-subtracter — In digital circuits, an adder subtracter is a circuit that is capable of adding or subtracting numbers (in particular, binary).Below is a circuit that does adding or subtracting depending on a control signal.However, it is possible to construct a … Wikipedia
DLX-Mikroprozessor — Der DLX Mikroprozessor ist eine hypothetische Prozessorarchitektur die von John L. Hennessy und David A. Patterson (den ursprünglichen Designern der MIPS und Berkeley RISC Architektur) entwickelt wurde. Er wurde in dem – von beiden gemeinsam … Deutsch Wikipedia
NEC µPD7720 — The NEC µPD7720 is the name of fixed point digital signal processors from NEC (currently Renesas Electronics). It was introduced in 1980, at which time it was the first commercial DSP in the industry. The NEC µPD7720 runs at 4 MHz frequency… … Wikipedia
Memory-mapped I/O — For more generic meanings of input/output port, see Computer port (hardware). MMIO redirects here. For the airport serving Saltillo, Mexico, assigned the ICAO code MMIO, see Plan de Guadalupe International Airport. Memory mapped I/O (MMIO) and… … Wikipedia
Intel Atom — Z520 compared to a 1 Eurocent coin. It is 182 mm2.[1] Produced 2008–present Common manufacturer(s) … Wikipedia
DLX — Der DLX Mikroprozessor ist eine hypothetische Prozessorarchitektur die von John L. Hennessy und David A. Patterson (den ursprünglichen Designern der MIPS und Berkeley RISC Architektur) entwickelt wurde. Er wurde in dem von beiden gemeinsam… … Deutsch Wikipedia